Method for forming a self-aligned isolation trench

ABSTRACT

The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross section of which has a nail shape in cross section.

[0001] This is a continuation of U.S. patent application Ser. No.08/985,588, filed on Dec. 5, 1997, which is a divisional patentapplication of U.S. patent application Ser. No. 08/823,609, filed onMar. 25, 1997, both of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. The Field of the Invention

[0003] The present invention relates to forming an isolation trench in asemiconductor device. In particular, the present invention relates to amethod of forming an isolation trench in an etching process for asemiconductor device that combines a spacer etch with a trench etch.

[0004] 2. The Relevant Technology

[0005] An isolation trench is used in an active area associated with amicroelectronic device on a semiconductor substrate or on a substrateassembly. Isolation trenches allow microelectronics devices to be placedincreasingly closer to each other without causing detrimental electronicinteraction such as unwanted capacitance build-up and cross-talk. In thecontext of this document, the term semiconductive substrate is definedto mean any construction comprising semiconductive material, includingbut not limited to bulk semiconductive material such as a semiconductivewafer, either alone or in assemblies comprising other materials thereon,and semiconductive material layers, either alone or in assembliescomprising other materials. The term substrate refers to any supportingstructure including but not limited to the semiconductive substratesdescribed above. The term substrate assembly is intended herein to meana substrate having one or more layers or structures formed thereon. Assuch, the substrate assembly may be, by way of example and not by way oflimitation, a doped silicon semiconductor substrate typical of asemiconductor wafer.

[0006] The ever-present pressure upon the microelectronics industry toshrink electronic devices and to crowd a higher number of electronicdevices onto a single die, called miniaturization, has required the useof such structures as isolation trenches.

[0007] In the prior state of the art, an etching process of fillmaterial within an isolation trench has been problematic. As seen inFIG. 1, a semiconductor substrate 12 has an isolation trenchsubstantially filled up with an isolation material 48. A pad oxide 14 issituated on the active area of semiconductor substrate 12. Isolationmaterial 48 exhibits a non-planarity at the top surface thereof betweencorners 62, particularly as is seen at reference numeral 46 in FIG. 1.The non-planarity of the top surface of isolation material 48 is due todissimilarity of etch rates between isolation material 48 and pad oxide14, particularly at corners 62 of the active area of semiconductorsubstrate 12.

[0008] An active area may be formed within semiconductor substrate 12immediately beneath pad 14, and adjacent isolation material 48. Aproblem that is inherent in such non-planarity of fill material withinan isolation trench is that corners 62 may leave the active area ofsemiconductor substrate 12 exposed. As such, isolation material 48 willnot prevent layers formed thereon from contacting the active area ofsemiconductor substrate 12 at corners 62. Contact of this sort isdetrimental in that it causes charge and current leakage. Isolationmaterial 48 is also unable to prevent unwanted thermal oxideencroachment through corners 62 into the active area of semiconductorsubstrate 12.

[0009] What is needed is a method of forming an isolation trench, wheresubsequent etching of fill material within the isolation trench of suchmethod prevents overlying layers from having contact with an adjacentactive area, and prevents unwanted thermal oxide encroachment into theactive area. What is also needed is a method of forming an isolationtrench wherein etching or planarizing such as by chemical mechanicalplanarization (CMP) of isolation trench materials is accomplishedwithout forming a recess at the intersection of the fill material in theisolation trench and the material of the active area within thesemiconductor substrate.

SUMMARY OF THE INVENTION

[0010] The present invention relates to a method for forming anisolation trench structure on a semiconductor substrate. The inventivemethod forms and fills the isolation trench without causing deleterioustopographical depressions in the upper surface of the fill material inthe isolation trench, while substantially preventing contact betweenlayers overlying the fill material of the isolation trench and theactive area of the semiconductor substrate. By avoiding such deleterioustopographical depressions and the exposure of the active area,detrimental charge and current leakage is minimized.

[0011] The inventive method of forming an isolation trench comprisesforming a pad oxide upon a semiconductor substrate and depositing afirst dielectric layer thereupon. By way of non-limiting example, thefirst dielectric layer is a nitride layer. The first dielectric layer ispatterned and etched with a mask to expose a portion of the pad oxidelayer and to protect an active area in the semiconductor substrate thatremains covered with the first dielectric layer. A second dielectriclayer is formed substantially conformably over the pad oxide layer andthe remaining portions of the first dielectric layer.

[0012] A spacer etch is used to form a spacer from the second dielectriclayer. The spacer electrically insulates the first dielectric layer. Anisolation trench etch follows the spacer etch and creates within thesemiconductor substrate an isolation trench that is defined by surfacesin the semiconductor substrate. The spacer formed by the spacer etchfacilitates self-alignment of the isolation trench formed by theisolation trench etch. The isolation trench etch can be carried out withthe same etch recipe as the spacer etch, or it can be carried out withan etch recipe that is selective to the spacer. Once the isolationtrench is formed, an insulation liner on the inside surface of theisolation trench can be optionally formed, either by deposition or bythermal oxidation.

[0013] A third dielectric layer is formed substantially conformably overthe spacer and the first dielectric layer so as to substantially fillthe isolation trench. Topographical reduction of the third dielectriclayer follows, preferably so as to planarize the third dielectric layerfor example by chemical mechanical planarizing (CMP), by dry etchback,or by a combination thereof.

[0014] The topographical reduction of the third dielectric layer mayalso be carried out as a single etchback step that sequentially removessuperficial portions of the third dielectric layer that extend out ofthe isolation trench. The single etchback also removes portions of theremaining spacer, and removes substantially all of the remainingportions of the first dielectric layer. Preferably, the single etchbackwill use an etch recipe that is more selective to the third dielectriclayer and the spacer than to the remaining portions of the firstdielectric layer. The single etchback uses an etch recipe having aselectivity that will preferably leave a raised portion of the thirddielectric layer extending above the isolation trench while removingsubstantially all remaining portions of the first dielectric layer. Theresulting structure can be described as having the shape of a nail asviewed in a direction that is substantially orthogonal to the crosssection of a word line in association therewith.

[0015] Several other processing steps are optional in the inventivemethod. One such optional processing step is the deposition of apolysilicon layer upon the pad oxide layer to act as an etch stop orplanarization marker. Another optional processing step includes clearingthe spacer following the isolation trench etch. An additional optionalprocessing step includes implanting doping ions at the bottom of theisolation trench to form a doped trench bottom. When a CMOS device isbeing fabricated, the ion implantation process may require a partialmasking of the semiconductor substrate so as to properly dope selectedportions of the semiconductor substrate.

[0016] These and other features of the present invention will becomemore fully apparent from the following description and appended claims,or may be learned by the practice of the invention as set forthhereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order that the manner in which the above-recited and otheradvantages of the invention are obtained, a more particular descriptionof the invention briefly described above will be rendered by referenceto specific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be considered tobe limiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

[0018]FIG. 1 illustrates the prior art problem of an uneven etch of anisolation trench that results in exposing portions of an active area andunwanted thermal oxide encroachment into the active area.

[0019]FIG. 2A is an elevational cross-section view of a semiconductorsubstrate, wherein a pad oxide and a nitride layer have been depositedupon the semiconductor substrate.

[0020]FIG. 2B is an elevational cross-section view of a semiconductorsubstrate having thereon a polysilicon layer that has been depositedupon a pad oxide, and a nitride layer that has been deposited upon thepolysilicon layer.

[0021]FIG. 3A illustrates further processing of the structure depictedin FIG. 2A, wherein a mask has been patterned and the nitride layer hasbeen etched down to the pad oxide layer to form a nitride island overfuture or current active areas in the substrate that are to beprotected.

[0022]FIG. 3B illustrates further processing of the structure depictedin FIG. 2B, wherein a mask has been patterned and the nitride layer hasbeen etched down through the nitride layer and the polysilicon layer tostop on the pad oxide layer, thereby forming a nitride island and apolysilicon island over future or current active areas in the substratethat are to be protected.

[0023]FIG. 4A is a view of further processing of FIG. 3A, wherein themask has been removed and an insulation film has been deposited over thenitride island.

[0024]FIG. 4B illustrates further processing of the structure in FIG.3B, wherein the mask has been removed and an insulation film has beendeposited over the nitride island and the polysilicon island.

[0025]FIGS. 5A and 5B illustrate further processing of the structuredepicted, respectively, in FIGS. 4A and 4B, in which the insulation filmhas been etched to form a spacer, a simultaneous or serial etch hasformed an isolation trench, thermal oxidation or deposition within theisolation trench has formed an insulation liner therein, and wherein anoptional ion implantation has formed a doped region at the bottom of theisolation trench.

[0026]FIGS. 6A and 6B illustrate further processing of the structuredepicted, respectively, in FIGS. 5A and 5B, in which an isolation filmhas been deposited over the spacer, the isolation trench within theisolation trench liner, and the nitride island.

[0027]FIGS. 7A and 7B illustrate further processing of the structuredepicted, respectively, in FIGS. 6A and 6B, wherein a planarizationprocess has formed a first upper surface made up of the nitride island,the spacer, and the isolation film, all being substantially co-planar onthe first upper surface.

[0028]FIG. 8A illustrates further processing of the structure depictedin FIGS. 7A or 9A, wherein the semiconductor substrate has beenimplanted with ions, and wherein the isolation film, optionally the padoxide layer, the insulation liner, and the spacer have fused to form aunitary isolation structure.

[0029]FIG. 8B illustrates optional further processing of the structuredepicted in FIG. 6B, wherein an etching process using an etch recipethat is slightly selective to oxide over nitride, has etched back theisolation film, the nitride island, and the spacer to expose thepolysilicon island, and has formed a filled isolation trench which, whenviewed in a direction that is substantially orthogonal to the crosssection of the depicted word line, has the shape of a nail.

[0030]FIG. 9A illustrates optional further processing of the structuredepicted in FIG. 6A or in FIG. 7A, wherein an etch-selective recipe thatis slightly selective to oxide over nitride has formed a filledisolation trench which, when viewed in cross section, has the shape of anail.

[0031]FIG. 9B illustrates further processing of the structure depictedin either FIGS. 7B or 8B wherein the semiconductor substrate has beenimplanted with ions, and wherein the isolation film, optionally the padoxide layer, the insulation liner, and the spacer have been fused toform a filled isolation trench.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The present invention relates to a method for forming aself-aligned isolation trench. The isolation trench is preferably ashallow trench isolation region that is self-aligned to an underlyingactive area. Stated otherwise, the inventive method forms a Narrowself-aligned Active area Isolation region that is inherently Level(NAIL). In the method of the present invention, a spacer etch and anisolation trench etch can be accomplished essentially within the sameprocessing step.

[0033] Another aspect of the present invention relates to a combinednitride and oxide etch that is selective to polysilicon, and in whichselectivity of the etch between nitride and oxide materials favors oneor the other by a factor of about one half. A still further aspect ofthe present invention relates to the use of a polysilicon film as anetch stop or planarization marker film. The structure achieved by themethod of the present invention achieves particular advantages thatovercome problems of the prior art.

[0034] A starting structure for an example of a first embodiment of thepresent invention is illustrated in FIG. 2A. In FIG. 2A, a pad oxide 14is grown upon a semiconductor substrate 12 on a semiconductor structure10. Semiconductor substrate 12 can be substantially composed of silicon.Following growth of pad oxide 14, a nitride layer 16 is deposited oversemiconductor substrate 12. FIG. 2A illustrates deposition of nitridelayer 16 upon pad oxide 14.

[0035]FIG. 3A illustrates a step in the formation of an isolation trenchby the method of the present invention. Nitride layer 16 is patternedwith a mask 20. An anisotropic etch selectively removes portions ofnitride layer 16. FIG. 3A illustrates the result of etching with the useof mask 20, wherein nitride layer 16 has formed an insulator island 22,as seen in FIG. 4A. Insulator island 22 is patterned over and protectsfuture or current active areas (not pictured) in semiconductor substrate12 during isolation trench processing. Following etch of nitride layer16, mask 20 is removed.

[0036]FIG. 4A illustrates further processing of the structure depictedin FIG. 3A, wherein an insulation film 26 has been deposited uponinsulator island 22 and exposed portions of pad oxide 14. Insulationfilm 26 can be an oxide such as silicon dioxide, and can be formed forexample by decomposition of tetraethyl ortho silicate (TEOS). Insulationfilm 26 may also be formed by a plasma enhanced chemical vapordeposition (PECVD) process so as to deposit a nitride layer such asSi₃N₄ or equivalent. When insulation film 26 is a nitride layer,insulator island 22 would be selected to be composed of a substantiallydifferent material, such as an oxide. Formation of substantiallydifferent materials between insulator island 22 and insulation film 26facilitate selective etchback or selective mechanical planarization suchas chemical-mechanical polishing (CMP) in the inventive method offorming an isolation trench.

[0037] Following deposition of insulation film 26, a spacer etch and anisolation trench etch are carried out. The spacer etch and the isolationtrench etch can be carried out with a single etch recipe that isselective to insulation film 26. Alternatively, the spacer etch and theisolation trench etch can be carried out with two etch recipes. As such,the first etch etches insulation film 26 in a spacer etch that forms aspacer 28 seen in FIG. 5A. The second etch, or isolation trench etch,has an etch recipe that is selective to spacer 28 and insulator island22, and anisotropically etches an isolation trench 32 having a side wall50 in semiconductor substrate 12.

[0038] Spacer 28 may facet during the spacer etch such that asubstantially linear spacer profile is achieved. Spacer 28 adds theadvantage to the inventive process of extending the lateral dimension ofthe active area that is to be formed within semiconductor substrate 12immediately beneath insulator island 22. Because spacer 28 takes uplateral space that would otherwise be available for isolation trench 32,isolation trench 32 is made narrower and the active area that is to beformed within semiconductor substrate 12 is made wider.

[0039] Following the formation of isolation trench 32, sidewall 50 ofisolation trench 32 has optionally formed thereon an insulation liner30. For example, thermal oxidation of sidewall 50 will form insulationliner 30 within isolation trench 32. Insulation liner 30 will preferablybe substantially composed of silicon dioxide. In FIG. 5A it can be seenthat, following thermal oxidation of sidewall 50 to form insulationliner 30 within isolation trench 32, semiconductor substrate 12 forms arounded edge at the top of isolation trench 32. Rounding of the top ofsemiconductor substrate 12 at the corners of isolation trench 32provides an added advantage of further isolating semiconductor substrate12 immediately beneath insulator island 22; thereby an active area thatwill form in semiconductor substrate 12 immediately under insulatorisland 22 will be further isolated. The feature of rounding of thecorners of semiconductor substrate 12 at the tops of isolation trenches32 as depicted in FIGS. 5A and 5B is presupposed in all embodiments ofthe present invention as a preferred alternative.

[0040] Another method of forming insulation liner 30 is CVD of adielectric material, or a dielectric material precursor that depositspreferentially upon sidewall 50 of isolation trench 32. The material ofwhich insulation liner 30 is substantially composed may be particularlyresistant to further etching, cleaning, or other processing conditions.

[0041] Insulation liner 30 may be substantially composed of a nitridesuch as Si₃N₄, or an equivalent, and can be selectively formed uponsidewall 50 of isolation trench 32. When semiconductor substrate 12immediately adjacent to isolation trench 32 is a doped monocrystallinesilicon that forms, for example, an active area for a transistorsource/drain region, oxidation is avoided therein by insulation liner30. Insulation liner is preferably substantially composed of Si₃N₄ or anon-stoichiometric variant which seals sidewall 50 so as to preventencroachment of oxide into semiconductor substrate 12.

[0042] Following formation of insulation liner 30, ion implantation isoptionally carried out to form a doped trench bottom 34 at the bottom ofisolation trench 32. For example, if semiconductor wafer 10 comprises anN-doped silicon substrate, implantation of P-doping materials at thebottom of isolation trench 32 will form a P-doped trench bottom 34. Ionimplantation may be carried out in a field implantation mode. If acomplementary metal oxide semiconductor (CMOS) is being fabricated,however, masking of complimentary regions of semiconductor substrate 12is required in order to achieve the differential doping thereof. For anN-doped silicon substrate, a high breakdown voltage may be achieved byP-doping. A low breakdown voltage may achieved by N-doping, and anintermediate breakdown voltage may be achieved by no doping. Because thepresent invention relates to formation of isolation trenches, P-dopingin an N-well region, or N-doping in a P-well region are preferred.

[0043] Preferably, implantation of P-doping ions is carried out to formdoped trench bottom 34 in a direction that is substantially orthogonalto the plane of pad oxide 14. Slightly angled implantation ofP-implantation ions may be carried out to enrich or broaden theoccurrence of P-doping ions in doped trench bottom 34 at the bottom ofisolation trench 32. If P-doping is carried out where semiconductorsubstrate 12 is N-doped, care must be taken not to dope throughinsulation liner 30 on sidewall 50 near pad oxide 14, which may causedetrimental deactivation of active areas (not shown) in semiconductorsubstrate 12.

[0044] Following optional implantation of doping ions, it may bedesirable, depending upon the intended shape and design of the isolationtrench, to remove all or a portion of spacer 28. The isolation trenchformed by the inventive method, however, will preferably include atleast a portion of spacer 28 that extends away from the isolation trench32.

[0045] As seen in FIG. 6A, isolation trench 32 is filled by an isolationfilm 36 which also is formed upon insulator island 22. Isolation film 36can formed by a deposition process using, for example, TEOS as aprecursor.

[0046] An optional processing step of the inventive method is to fusetogether spacer 28, pad oxide 14, and isolation film 36. The processingtechnique for such fusion is preferably a heat treatment ofsemiconductor structure 10. If such fusion is contemplated, it is alsodesirable that spacer 28, pad oxide 14, and isolation film 36 all becomposed of substantially the same material, as fusion is bestfacilitated with common materials.

[0047] It is preferable, at some point in fabrication of the isolationtrench, to densify the fill material of the isolation trench.Densification is desirable because it helps to prevent separation ofmaterials in contact with the fill material. As seen in FIG. 6A,densification will prevent isolation film 36 from separating atinterfaces with spacer 28, pad oxide layer 14, and insulation liner 30.It is preferable to perform densification of isolation film 36immediately following its deposition. Depending upon the specificapplication, however, densification may be carried out at other stagesof the process. For example, densification of isolation film 36 by rapidthermal processing (RTP) may make either etchback or CMP more difficult.As such, it is preferable to densify later in the fabrication process,such as after planarizing or etchback processing.

[0048]FIG. 7A illustrates a subsequent step of formation of theisolation trench wherein insulator island 22, spacer 28, and isolationfilm 36 are planarized to a common co-planar first upper surface 38.First upper surface 38 will preferably be formed by a CMP or etchbackprocess. Preferably, planarization will be selective to isolation film36, and relatively slightly selective to insulator island 22, such as bya factor of about one half. A first preferred selectivity of an etchrecipe used in the inventive method is in the range of about 1:1 toabout 2:1, selective to isolation film 36 as compared to insulatorisland 22. A more preferred selectivity is in the range of about 1.3:1to about 1.7:1. A most preferred selectivity is about 1.5:1.Planarization also requires the etch recipe to be slightly selective tospacer 28 over insulator island 22. Preferably spacer 28 and isolationfilm 36 are made from the same material such that the etch will besubstantially uniform as to the selectivity thereof with respect tospacer 28 and isolation film 36 over insulator island 22.

[0049] First upper surface 38 is illustrated as being substantiallyplanar in FIG. 7A. It will be appreciated by one of ordinary skill inthe art that first upper surface 38 will form a non-planar profile ortopography depending upon the selectivity of the etch recipe or of thechemical used in a planarization technique such as CMP. For example,where reduced island 52 is formed from a nitride material and isolationfilm 36 is formed from an oxide material, first upper surface 38 wouldundulate as viewed in cross section with more prominent structures beingthe result of an etch or planarization technique more selective thereto.

[0050] In FIG. 7A, reduced island 52 has been formed from insulatorisland 22. Additionally, portions of isolation film 36 and spacer 28remain after planarization. Reduced island 52 preferably acts as apartial etch stop.

[0051]FIG. 8A illustrates the results of removal of reduced island 52.Reduced island 52 is preferably removed with an etch that is selectiveto isolation film 36 and spacer 28, leaving an isolation structure 48that extends into and above isolation trench 32, forming a nail shapedstructure having a head 54 extending above and away from isolationtrench 32 upon an oxide layer 44. The future or current active area ofsemiconductor substrate 12, which may be at least partially covered overby head 54, is substantially prevented from a detrimental charge andcurrent leakage by head 54.

[0052] Phantom lines 60 in FIG. 8A illustrate remnants of pad oxidelayer 14, insulation liner 30, and spacer 28 as they are optionallythermally fused with isolation film 36 to form isolation structure 48.Isolation structure 48, illustrated in FIG. 8A, comprises a trenchportion and a flange portion which together, when viewed in crosssection, form the shape of a nail.

[0053] The trench portion of isolation structure 48 is substantiallycomposed of portions of isolation film 36 and insulation liner 30. Thetrench portion intersects the flange portion at a second upper surface40 of semiconductor substrate 12 as seen in FIG. 8A. The trench portionalso has two sidewalls 50. FIG. 8A shows that the trench portion issubstantially parallel to a third upper surface 42 and sidewalls 50. Theflange portion is integral with the trench portion and is substantiallycomposed of portions of pad oxide layer 14, spacer 28, and isolationfilm 36. The flange portion has a lowest region at second upper surface40 where the flange portion intersects the trench portion. The flangeportion extends above second upper surface 40 to third upper surface 42seen in FIG. 8A. Upper surfaces 40, 42 are substantially orthogonal totwo flange sidewalls 64 and sidewall 50. The flange portion issubstantially orthogonal in orientation to the trench portion. Theflange portion may also include a gate oxide layer 44 after gate oxidelayer 44 is grown.

[0054] Following formation of isolation structure 48, it is often usefulto remove pad oxide 14, seen in FIG. 8A, due to contamination thereofduring fabrication of isolation structure 48. Pad oxide 14 can becomecontaminated when it is used as an etch stop for removal of reducedisland 52. For example, pad oxide 14 may be removed by using aqueous HFto expose second upper surface 40. A new oxide layer, gate oxide layer44, may then be formed on second upper surface 40 having third uppersurface 42.

[0055] Semiconductor structure 10 may be implanted with ions asillustrated by arrows seen in FIG. 8A. This implantation, done withN-doping materials in an N-well region, for example, is to enhance theelectron conductivity of the active area (not shown) of semiconductorsubstrate 12. Either preceding or following removal of pad oxide 14 seenin FIG. 8A, an enhancement implantation into the active area ofsemiconductor substrate 12 may be carried out, whereby preferred dopingions are implanted on either side of isolation structure 48.

[0056] Ion implantation into semiconductor substrate 12 to form activeareas, when carried out with isolation structure 48 in place, will causean ion implantation concentration gradient to form in the region ofsemiconductor substrate 12 proximate to and including second uppersurface 40. The gradient will form within semiconductor substrate 12near second upper surface 40 and immediately beneath the flangesidewalls 64 as the flange portion of isolation structure 48 willpartially shield semiconductor substrate 12 immediately therebeneath.Thus, an ion implant gradient will form and can be controlled in part bythe portion of semiconductor substrate 12 that is covered by head 54.

[0057] Gate oxide layer 44 is formed upon second upper surface 40 afterpad oxide 14 has been removed to form portions of third upper surface42. The entirety of third upper surface 42 includes head 54 of isolationstructure 48 as it extends above gate oxide layer 44 and gate oxidelayer 44.

[0058] In a variation of the first embodiment of the present invention,the structure illustrated in FIG. 6A is planarized by use of a singleetchback process. The single etchback uses an etch recipe that has adifferent selectivity for insulator island 22 than for isolation film36. In this alternative embodiment, spacer 28, dielectric film 36, andpad oxide 14 are composed of substantially the same material. Insulatorisland 22 has a composition different from that of isolation film 36.For example, isolation film 36 and spacer 28 are composed of SiO₂, andinsulator island 22 is composed of silicon nitride.

[0059] The etch recipe for the single etchback is chosen to be selectiveto isolation film 36 such that, as upper surface 58 of isolation film 36recedes toward pad oxide 14 and eventually exposes insulator island 22and spacer 28, insulator island 22 has a greater material removal ratethan spacer 28 or isolation film 36. As such, a final isolationstructure 48 illustrated in FIG. 9A is achieved. Pad oxide 14 acts as anetch stop for this etch recipe. A residual depression of isolation film36 may appear centered over filled isolation trench 32. A depressionwould be created, centered above isolation trench 32, during the fillingof isolation trench 32 with isolation film 36, as seen in FIG. 6A. Wherea depression is not detrimental to the final isolation structure 48 asillustrated in FIG. 9A, this selective etch recipe alternative may beused.

[0060] Semiconductor structure 10, as illustrated in FIG. 9A, can beseen to have a substantially continuous isolation structuresubstantially covering semiconductor substrate 12. An upper surface 42 aof isolation structure 48 includes the head portion or nail head 54.Semiconductor substrate 12 is covered at an upper surface 42 b by eithera pad oxide layer or a gate oxide layer. Another upper surface 42 ccomprises the upper surface of the pad oxide layer or gate oxide layer.

[0061] A starting structure for an example of a second embodiment of thepresent invention is illustrated in FIG. 2B. In FIG. 2B, pad oxide layer14 is grown upon semiconductor substrate 12 and a polysilicon layer 18is deposited upon pad oxide layer 14. This embodiment of the presentinvention parallels the processing steps of the first embodiment withthe additional processing that takes into account the use of polysiliconlayer 18.

[0062]FIG. 3B illustrates etching through nitride layer 16 andpolysilicon layer 18 to stop on pad oxide layer 14. The etch createsboth an insulator island 22 and a polysilicon island 24 formed,respectively, from nitride layer 16 and polysilicon layer 18.

[0063]FIG. 4B illustrates further processing of the structure depictedin FIG. 3B, wherein insulation film 26 has been deposited upon insulatorisland 22, laterally exposed portions of polysilicon island 24, andexposed portions of pad oxide layer 14. Following deposition ofinsulation film 26, a spacer etch and an isolation trench etch arecarried out similarly to the spacer etch and isolation trench etchcarried out upon semiconductor structure 10 illustrated in FIG. 5A.

[0064]FIG. 5B illustrates the results of both the spacer etch and theisolation trench etch and optional implantation of isolation trench 32to form doped well 34 analogous to doped trench bottom 34 illustrated inFIG. 5A. Formation of insulation liner 30 within isolation trench 32preferentially precedes implantation to form doped trench bottom 34.Following optional implantation of doping ions, full or partial removalof spacer 28 may optionally be performed as set forth above with respectto the first embodiment of the invention.

[0065]FIG. 6B illustrates a subsequent step in fabrication of anisolation trench according to the second embodiment of the inventivemethod, wherein isolation film 36 is deposited both within isolationtrench 32, and over both of insulator island 22 and spacer 28. As setforth above, densification of isolation film 36 is a preferred step tobe carried out either at this stage of fabrication or at a subsequentselective stage. Planarization or etchback of isolation film 36 is nextcarried out as set forth in the first embodiment of the presentinvention, and as illustrated in FIG. 7B.

[0066] The process of planarization or etchback of isolation film 36reduces insulator island 22 to form reduced island 52 as illustrated inFIG. 7B. Next, additional selective ion implantations can be madethrough polysilicon island 24 and into the active area of semiconductorsubstrate 12 that lies beneath polysilicon island 24.

[0067] In FIG. 8B, it can be seen in phantom that spacer 28 has a topsurface that is co-planar with third upper surface 42 of isolationstructure 48 after planarization. Polysilicon island 24 and spacer 28are formed as shown in FIG. 8B. Removal of spacer 28 from the structuresillustrated in FIG. 8B can be accomplished by patterning and etchingwith a mask that covers head 54 that extends above and away fromisolation trench 32 seen in FIG. 8B. The etching process exposes asurface on semiconductor substrate 12 upon which a gate oxide layer isdeposited or grown.

[0068] To form the structure seen in FIG. 9B, semiconductor structures10 of FIGS. 7B or 8B are subjected to implantation of semiconductorsubstrate 12 with ions. Semiconductor structure 10 is then subjected toa heat treatment so as to fuse together isolation film 36, optional padoxide layer 14, insulation liner 60, and spacer 28 into an integralfilled isolation trench.

[0069] Subsequent to the process illustrated in FIGS. 6A-8A and 6B-9B afinal thermal treatment, or subsequent thermal treatments, can beperformed. Heat treatment may cause isolation structure 48 to be widerproximal to upper surface 42 than proximal to doped trench bottom 34.When so shaped, an unoxidized portion of the active area ofsemiconductor substrate 12 that forms sidewall 50 would have atrapezoidal shape when viewed in cross section, where the widest portionis upper surface 40 and the narrowest portion is at doped trench bottom34. Where a trapezoidal shape of the trench portion causes unwantedencroachment into the active area of semiconductor substrate 12, theoptional formation of insulation liner 30 from a nitride material orequivalent is used to act as an oxidation barrier for sidewall 50.Semiconductor structure 10 is illustrated in FIG. 9B as being implantedby doping ions, as depicted with downwardly-directed arrows. Following apreferred implantation, thermal processing may be carried out in orderto achieve dopant diffusion near upper surface 42 b of implanted ionsresiding within semiconductor substrate 12. Due to head 54 extendingonto semiconductor substrate 12, a doping concentration gradient can beseen between the active area 53 a and the active area 53 b. The startingand stopping point of the doping concentration gradient in relation toflange sidewalls 64 will depend upon the duration and temperature of athermal treatment.

[0070] The present invention may be carried out wherein spacer 28 andisolation film 36 are substantially composed of the same oxide material,and insulator island 22 is substantially composes of a nitridecomposition. Other compositions may be chosen wherein etch selectivityor CMP selectivity slightly favors insulator island 22 over both spacer28 and isolation film 36. The specific selection of materials willdepend upon the application during fabrication of the desired isolationtrench.

[0071] The present invention may be embodied in other specific formswithout departing from its spirit or essential characteristics. Thedescribed embodiments are to be considered in all respects only asillustrated and not restrictive. The scope of the invention is,therefore, indicated by the appended claims and their combination inwhole or in part rather than by the foregoing description. All changesthat come within the meaning and range of equivalency of the claims areto be embraced within their scope.

What is claimed and desired to be secured by United States LettersPatent is:
 1. A method of forming a microelectronic structure, themethod comprising: forming an oxide layer upon a semiconductorsubstrate; forming a first dielectric layer upon said oxide layer;selectively removing said first dielectric layer to expose said oxidelayer at a plurality of areas; forming a second dielectric layer oversaid oxide layer and said first dielectric layer; selectively removingsaid second dielectric layer to form a plurality of spacers from saidsecond dielectric layer, wherein each said spacer is situated upon saidoxide layer, is in contact with said first dielectric layer, and isadjacent to an area of said plurality of areas; forming a plurality ofisolation trenches extending below said oxide layer into saidsemiconductor substrate, wherein each said isolation trench is adjacentto and below a pair of said spacers and is situated at a correspondingarea of said plurality of areas; filling each said isolation trench witha conformal layer, said conformal layer extending above said oxide layerin contact with a corresponding pair of said spacers; planarizing theconformal layer and each said spacer to form therefrom an upper surfacefor each said isolation trench that is co-planar to the other said uppersurfaces; wherein material that is electrically insulative extendscontinuously between and within said plurality of isolation trenches. 2.A method according to claim 1 , further comprising forming a liner upona sidewall of each said isolation trench.
 3. A method according to claim2 , wherein said a liner is a thermally grown oxide of saidsemiconductor substrate.
 4. A method according to claim 2 , whereinforming said liner upon said sidewall of said isolation trench comprisesdeposition of a composition of matter.
 5. A method according to claim 1, further comprising forming a doped region below the termination ofeach said isolation trench within said semiconductor substrate.
 6. Amethod according to claim 1 , wherein said upper surface for each saidisolation trench is formed by chemical mechanical planarization.
 7. Amethod of forming a microelectronic structure, the method comprising:forming an oxide layer upon a semiconductor substrate; forming a firstdielectric layer upon said oxide layer; selectively removing said firstdielectric layer to expose said oxide layer at a plurality of areas;forming a second dielectric layer over said oxide layer and said firstdielectric layer; selectively removing said second dielectric layer toform a plurality of spacers from said second dielectric layer, whereineach said spacer is situated upon said oxide layer, is in contact withsaid first dielectric layer, and is adjacent to an area of saidplurality of areas; forming a plurality of isolation trenches extendingbelow said oxide layer into said semiconductor substrate, wherein eachsaid isolation trench is adjacent to and below a pair of said spacersand is situated at a corresponding area of said plurality of areas;filling each said isolation trench with a conformal layer, saidconformal layer extending above said oxide layer in contact with acorresponding pair of said spacers; planarizing the conformal layer toform therefrom an upper surface for each said isolation trench that isco-planar to the other said upper surfaces, wherein: material that iselectrically insulative extends continuously between and within saidplurality of isolation trenches; said conformal layer and said spacersform said upper surface for each said isolation trench, each said uppersurface being formed from said conformal layer and said spacer and beingsituated above said pad oxide layer; and said first dielectric layer isin contact with at least a pair of said spacers and said pad oxidelayer.
 8. A method according to claim 7 , further comprising: removingsaid pad oxide layer upon a portion of a surface of said semiconductorsubstrate; and forming a gate oxide layer upon said portion of saidsurface of said semiconductor substrate.
 9. A method according to claim7 , wherein said upper surface for each said isolation trench is formedin an etch process using an etch recipe that etches said firstdielectric layer faster than said conformal layer and said spacers by aratio in a range from of about 1:1 to about 2:1.
 10. A method accordingto claim 9 , wherein said ratio is in a range from about 1.3:1 to about1.7:1.
 11. A method according to claim 7 , wherein said upper surfacefor each said isolation trench is formed by the steps comprising:chemical mechanical planarization, wherein said conformal layer, saidspacers, and said first dielectric layer form a planar first uppersurface; and an etch that forms a second upper surface, said secondupper surface being situated above said pad oxide layer.
 12. A methodaccording to claim 11 , wherein said etch uses an etch recipe thatetches said first dielectric layer faster than said conformal layer andsaid spacers by a ratio in a range from about 1:1 to about 2:1.
 13. Amethod according to claim 11 , wherein said ratio in a range from about1.3:1 to about 1.7:1.
 14. A method of forming a microelectronicstructure, the method comprising: forming an oxide layer upon asemiconductor substrate; forming a silicon nitride layer upon said oxidelayer; selectively removing said silicon nitride layer to expose saidoxide layer at a plurality of areas; forming a first silicon dioxidelayer over said oxide layer and over said silicon nitride layer;selectively removing said first silicon dioxide layer to form aplurality of spacers from said first silicon dioxide layer, wherein eachsaid spacer is situated upon said oxide layer, is contact with saidsilicon nitride layer, and is adjacent to an area of said plurality ofareas; forming a plurality of isolation trenches extending below saidoxide layer into and terminating within said semiconductor substrate,wherein each said isolation trench is adjacent to and below a pair ofsaid spacers and is situated at a corresponding area of said pluralityof areas; forming a corresponding electrically active region below thetermination of said each said isolation trench within said semiconductorsubstrate; forming a liner upon a sidewall of each said isolationtrench, said liner extending from an interface thereof with said oxidelayer to the termination of said isolation trench within saidsemiconductor substrate; filling each said isolation trench with asecond silicon dioxide layer, said second silicon dioxide layer withineach said isolation trench extending above said oxide layer in contactwith the corresponding pair of said spacers; and selectively removingsaid second silicon dioxide layer and said spacers to form an uppersurface for each said isolation trench that is co-planar to the othersaid upper surfaces and being situated above said pad oxide layer,wherein material that is electrically insulative extends continuouslybetween and within said plurality of isolation trenches.
 15. A methodaccording to claim 14 , wherein said a liner is a thermally grown oxideof said semiconductor substrate.
 16. A method according to claim 14 ,wherein said liner is composed of silicon nitride.
 17. A methodaccording to claim 15 , further comprising: removing said oxide layerupon a portion of a surface of said semiconductor substrate; and forminga gate oxide layer upon said portion of said surface of saidsemiconductor substrate.
 18. A method of a microelectronic structure,the method comprising: forming an oxide layer upon a semiconductorsubstrate; forming a polysilicon layer upon said oxide layer; forming afirst dielectric layer upon said polysilicon layer; selectively removingsaid first dielectric layer and said polysilicon layer to expose saidoxide layer at a plurality of areas; forming a second dielectric layerconformally over said oxide layer, said polysilicon layer, and saidfirst dielectric layer; selectively removing said second dielectriclayer to form a plurality of spacers from said second dielectric layer,wherein each said spacer is upon said oxide layer, is in contact withboth said polysilicon layer and said first dielectric layer, and isadjacent to an area of said plurality of areas; forming a plurality ofisolation trenches extending below said oxide layer into and terminatingwithin said semiconductor substrate, wherein each said isolation trenchis adjacent to and below a pair of said spacers and is situated at acorresponding area of said plurality of areas; filling each saidisolation trench with a conformal third layer, said conformal thirdlayer extending above said oxide layer in contact with a correspondingpair of said spacers; planarizing the conformal third layer to formtherefrom an upper surface for each said isolation trench that isco-planar to the other said upper surfaces; wherein material that iselectrically insulative extends continuously between and within saidplurality of isolation trenches; wherein planarizing the conformal thirdlayer to form therefrom said upper surface for each said isolationtrench that is co-planar to the other said upper surfaces furthercomprises planarizing said conformal third layer and each said spacer toform therefrom said co-planar upper surfaces.
 19. A method according toclaim 18 , wherein said upper surface for each said isolation trench isformed by chemical mechanical planarization.
 20. A method according toclaim 18 , further comprising forming a doped region below thetermination of each said isolation trench within said semiconductorsubstrate.
 21. A method according to claim 18 , further comprising,prior to filling each said isolation trench with said conformal thirdlayer, forming a liner upon a sidewall of each said isolation trenchthat extends from an interface thereof with said oxide layer to thetermination of said isolation trench within said semiconductorsubstrate, and wherein said conformal third layer is composed of anelectrically conductive material.
 22. A method according to claim 21 ,wherein said a liner is a thermally grown oxide of said semiconductorsubstrate.
 23. A method according to claim 21 , wherein forming saidliner upon said sidewall of each said isolation trench comprisesdeposition of a composition of matter.
 24. A method of a microelectronicstructure, the method comprising: forming an oxide layer upon asemiconductor substrate; forming a polysilicon layer upon said oxidelayer; forming a first dielectric layer upon said polysilicon layer;selectively removing said first dielectric layer and said polysiliconlayer to expose said oxide layer at a plurality of areas; forming asecond dielectric layer conformally over said oxide layer, saidpolysilicon layer, and said first dielectric layer; selectively removingsaid second dielectric layer to form a plurality of spacers from saidsecond dielectric layer, wherein each said spacer is upon said oxidelayer, is in contact with both said polysilicon layer and said firstdielectric layer, and is adjacent to an area of said plurality of areas;forming a plurality of isolation trenches extending below said oxidelayer into and terminating within said semiconductor substrate, whereineach said isolation trench is adjacent to and below a pair of saidspacers and is situated at a corresponding area of said plurality ofareas; filling each said isolation trench with a conformal third layer,said conformal third layer extending above said oxide layer in contactwith a corresponding pair of said spacers; planarizing the conformalthird layer to form therefrom an upper surface for each said isolationtrench that is co-planar to the other said upper surfaces; whereinmaterial that is electrically insulative extends continuously betweenand within said plurality of isolation trenches; wherein said uppersurface for each said isolation trench is formed from said conformalthird layer, said spacers, and said first dielectric layer.
 25. A methodof a microelectronic structure, the method comprising: forming an oxidelayer upon a semiconductor substrate; forming a polysilicon layer uponsaid oxide layer; forming a first dielectric layer upon said polysiliconlayer; selectively removing said first dielectric layer and saidpolysilicon layer to expose said oxide layer at a plurality of areas;forming a second dielectric layer conformally over said oxide layer,said polysilicon layer, and said first dielectric layer; selectivelyremoving said second dielectric layer to form a plurality of spacersfrom said second dielectric layer, wherein each said spacer is upon saidoxide layer, is in contact with both said polysilicon layer and saidfirst dielectric layer, and is adjacent to an area of said plurality ofareas; forming a plurality of isolation trenches extending below saidoxide layer into and terminating within said semiconductor substrate,wherein each said isolation trench is adjacent to and below a pair ofsaid spacers and is situated at a corresponding area of said pluralityof areas; filling each said isolation trench with a conformal thirdlayer, said conformal third layer extending above said oxide layer incontact with a corresponding pair of said spacers; planarizing theconformal third layer to form therefrom an upper surface for each saidisolation trench that is co-planar to the other said upper surfaces;exposing said oxide layer upon a portion of a surface of saidsemiconductor substrate; forming a gate oxide layer upon said portion ofsaid surface of said semiconductor substrate; forming a layer composedof polysilicon upon said gate oxide layer in contact with a pair of saidspacers; and selectively removing said third layer, said spacers andsaid layer composed of polysilicon to form a portion of at least one ofsaid upper surfaces; wherein material that is electrically insulativeextends continuously between and within said plurality of isolationtrenches.
 26. A method of a microelectronic structure, the methodcomprising: forming an oxide layer upon a semiconductor substrate;forming a polysilicon layer upon said oxide layer; forming a firstdielectric layer upon said polysilicon layer; selectively removing saidfirst dielectric layer and said polysilicon layer to expose said oxidelayer at a plurality of areas; forming a second dielectric layerconformally over said oxide layer, said polysilicon layer, and saidfirst dielectric layer; selectively removing said second dielectriclayer to form a plurality of spacers from said second dielectric layer,wherein each said spacer is upon said oxide layer, is in contact withboth said polysilicon layer and said first dielectric layer, and isadjacent to an area of said plurality of areas; forming a plurality ofisolation trenches extending below said oxide layer into and terminatingwithin said semiconductor substrate, wherein each said isolation trenchis adjacent to and below a pair of said spacers and is situated at acorresponding area of said plurality of areas; filling each saidisolation trench with a conformal third layer, said conformal thirdlayer extending above said oxide layer in contact with a correspondingpair of said spacers; planarizing the conformal third layer by an etchusing an etch recipe that etches said first dielectric layer faster thansaid conformal third layer and said spacers by a ratio in a range fromof about 1:1 to about 2:1 to form therefrom an upper surface for eachsaid isolation trench that is co-planar to the other said uppersurfaces; wherein material that is electrically insulative extendscontinuously between and within said plurality of isolation trenches.27. A method according to claim 26 , wherein said ratio is in a rangefrom about 1.3:1 to about 1.7:1.
 28. A method of a microelectronicstructure, the method comprising: forming an oxide layer upon asemiconductor substrate; forming a polysilicon layer upon said oxidelayer; forming a first dielectric layer upon said polysilicon layer;selectively removing said first dielectric layer and said polysiliconlayer to expose said oxide layer at a plurality of areas; forming asecond dielectric layer conformally over said oxide layer, saidpolysilicon layer, and said first dielectric layer; selectively removingsaid second dielectric layer to form a plurality of spacers from saidsecond dielectric layer, wherein each said spacer is upon said oxidelayer, is in contact with both said polysilicon layer and said firstdielectric layer, and is adjacent to an area of said plurality of areas;forming a plurality of isolation trenches extending below said oxidelayer into and terminating within said semiconductor substrate, whereineach said isolation trench is adjacent to and below a pair of saidspacers and is situated at a corresponding area of said plurality ofareas; filling each said isolation trench with a conformal third layer,said conformal third layer extending above said oxide layer in contactwith a corresponding pair of said spacers; planarizing the conformalthird layer to form therefrom an upper surface for each said isolationtrench that is co-planar to the other said upper surfaces; chemicalmechanical planarization of said conformal third layer, said spacers,and said first dielectric layer to form a planar first upper surface;and an etch that forms a planar second upper surface, said second uppersurface being situated above said oxide layer; wherein material that iselectrically insulative extends continuously between and within saidplurality of isolation trenches.
 29. A method according to claim 28 ,wherein said etch uses an etch recipe that etches said first dielectriclayer faster than said conformal third layer and said spacers by a ratioin a range from about 1:1 to about 2:1.
 30. A method of forming andfilling an isolation trench according to claim 28 , wherein said ratioin a range from about 1.3:1 to about 1.7:1.
 31. A method of forming amicroelectronic structure, the method comprising: forming a pad oxidelayer upon a semiconductor substrate; forming a polysilicon layer uponsaid oxide layer; forming a silicon nitride layer upon said polysiliconlayer; selectively removing said silicon nitride layer and saidpolysilicon layer to expose said oxide layer at a plurality of areas;forming a first silicon dioxide layer over said oxide layer and oversaid silicon nitride layer; selectively removing said first silicondioxide layer to form a plurality of spacers from said first silicondioxide layer, wherein each said spacer is situated upon said oxidelayer, is in contact with said silicon nitride layer and saidpolysilicon layer, and is adjacent to an area of said plurality ofareas; forming a plurality of isolation trenches extending below saidoxide layer into and terminating within said semiconductor substrate,wherein each said isolation trench is adjacent to and below a pair ofsaid spacers and is situated at a corresponding area of said pluralityof areas; forming a corresponding doped region below the termination ofeach said isolation trench within said semiconductor substrate; forminga liner upon a sidewall of each said isolation trench, each said linerextending from an interface thereof with said oxide layer to thetermination of said isolation trench within said semiconductorsubstrate; filling each said isolation trench with a second layer, saidsecond layer extending above said oxide layer in contact with acorresponding pair of said spacers; and planarizing said second layerand each of said spacers to form therefrom an upper surface for eachsaid isolation trench that is co-planar to the other said upper surfacesand is situated above said oxide layer; wherein material that iselectrically insulative extends continuously between and within saidplurality of isolation trenches.
 32. A method according to claim 31 ,wherein each said liner is a thermally grown oxide of said semiconductorsubstrate, and wherein said second layer is composed on an electricallyconductive material.
 33. A method according to claim 31 , wherein eachsaid liner is composed of silicon nitride, and wherein said second layeris composed on an electrically conductive material.
 34. A methodaccording to claim 31 , further comprising: exposing said oxide layerupon a portion of a surface of said semiconductor substrate; forming agate oxide layer upon said portion of said surface of said semiconductorsubstrate; and forming a layer composed of polysilicon upon said gateoxide layer in contact with a pair of said spacers, and selectivelyremoving said layer composed of polysilicon to form a portion of atleast one of said upper surfaces.
 35. A method for a microelectronicstructure, the method comprising: providing a semiconductor substratehaving a top surface with an oxide layer thereon; forming a polysiliconlayer upon said oxide layer; forming a first layer upon said polysiliconlayer; forming a plurality of isolation trenches having electricallyinsulative material extending continuously between and within saidplurality of isolation trenches, each said isolation trench: having aspacer composed of a dielectric material upon said oxide layer incontact with said first layer and said polysilicon layer; extending froman opening thereto at the top surface of said semiconductor substrateand below said oxide layer into and terminating within saidsemiconductor substrate adjacent to and below said spacer; having asecond layer filling said isolation trench and extending above saidoxide layer in contact with said spacer; and having a planar uppersurface formed from said second layer and said spacer and being situatedabove said oxide layer.
 36. The method as defined in claim 35 , furthercomprising: doping the semiconductor substrate with a dopant having afirst conductivity type; doping the semiconductor substrate below eachsaid isolation trench with a dopant having a second conductivity typeopposite the first conductivity type to form a doped trench bottom thatis below and in contact with a respective one of each said isolationtrench.
 37. The method as defined in claim 36 , wherein the doped trenchbottom has a width, each said the isolation trench has a width, and thewidth of each said doped trench bottom is greater than the width of therespective isolation trench.
 38. A method for a microelectronicstructure, the method comprising: providing a semiconductor substratehaving a top surface with an oxide layer thereon; forming a first layerupon said oxide layer; forming a plurality of isolation trenches havingelectrically insulative material extending continuously between andwithin said plurality of isolation trenches, each said isolation trench:having a spacer composed of a dielectric material upon said oxide layerin contact with said first layer; extending from an opening thereto atthe top surface of said semiconductor substrate and below said oxidelayer into and terminating within said semiconductor substrate adjacentto and below said spacer; having a second layer filling said isolationtrench and extending above said oxide layer in contact with said spacer;and having a planar upper surface formed from said second layer and saidspacer and being situated above said oxide layer.
 39. The method asdefined in claim 38 , further comprising: doping the semiconductorsubstrate with a dopant having a first conductivity type; and doping thesemiconductor substrate below each said isolation trench with a dopanthaving a second conductivity type opposite the first conductivity typeto form a doped trench bottom that is below and in contact with arespective one of said isolation trenches.
 40. The method as defined inclaim 39 , wherein: the doped trench bottom has a width; peach saidisolation trench has a width; and the width of each said doped trenchbottom is greater than the width of the respective isolation trench. 41.A method of a microelectronic structure, the method comprising:providing a semiconductor substrate having a top surface; forming firstand second isolation trenches each: extending into and being defined bythe semiconductor substrate; having an opening thereto at the topsurface of the semiconductor substrate; and extending below and beingcentered between a pair of spacers situated above the top surface of thesemiconductor substrate; and wherein: an electrically insulativematerial extends continuously between and within the first and secondisolation trenches; and a planar surface begins at the first isolationtrench and extends continuously to the second isolation trench.
 42. Amethod for a microelectronic structure, the method comprising: providinga semiconductor substrate having a top surface with an oxide layerthereon; forming a polysilicon layer upon said oxide layer; forming afirst layer upon said polysilicon layer; forming a first isolationstructure including: a first spacer composed of a dielectric materialupon said oxide layer in contact with said first layer and saidpolysilicon layer; a first isolation trench extending from an openingthereto at the top surface of said semiconductor substrate and belowsaid oxide layer into and terminating within said semiconductorsubstrate adjacent to and below said first spacer, wherein said firstspacer is situated on a side of said first isolation trench; a secondspacer composed of a dielectric material upon said oxide layer incontact with said first layer and said polysilicon layer, said secondspacer being situated on a side of said first isolation trench oppositethe side of said first spacer; forming a second isolation structureincluding: a first spacer composed of a dielectric material upon saidoxide layer in contact with said first layer and said polysilicon layer;a first isolation trench extending below said oxide layer into andterminating within said semiconductor substrate adjacent to and belowsaid first spacer of said second isolation structure, wherein said firstspacer of said second isolation structure is situated on a side of saidfirst isolation trench; a second spacer composed of a dielectricmaterial upon said oxide layer in contact with said first layer and saidpolysilicon layer, said second spacer of said second isolation structurebeing situated on a side of said first isolation trench opposite theside of said first spacer of said second isolation structure; forming anactive area located within said semiconductor substrate between saidfirst and second isolation structures; forming a second layer, composedof an electrically insulative material, filling said first and secondisolation trenches and extending continuously therebetween and abovesaid oxide layer in contact with said first and second spacers of saidrespective first and second isolation structures; and forming a planarupper surface from said second layer and said first and second spacersof said respective first and second isolation structures, and beingsituated above said oxide layer.
 43. A method of a microelectronicstructure, the method comprising: providing a semiconductor substratehaving a top surface with an oxide layer thereon; forming a first layerupon said oxide layer; forming a first isolation structure including: afirst spacer composed of a dielectric material upon said oxide layer incontact with said first layer; a first isolation trench extending froman opening thereto at the top surface of said semiconductor substrateand below said oxide layer into and terminating within saidsemiconductor substrate adjacent to and below said first spacer, whereinsaid first spacer is situated on a side of said first isolation trench;a second spacer composed of a dielectric material upon said oxide layerin contact with said first layer, said second spacer being situated on aside of said first isolation trench opposite the side of said firstspacer; forming a second isolation structure including: a first spacercomposed of a dielectric material upon said oxide layer in contact withsaid first layer; a first isolation trench extending below said oxidelayer into and terminating within said semiconductor substrate adjacentto and below said first spacer of said second isolation structure,wherein said first spacer of said second isolation structure is situatedon a side of said first isolation trench; a second spacer composed of adielectric material upon said oxide layer in contact with said firstlayer, said second spacer of said second isolation structure beingsituated on a side of said first isolation trench opposite the side ofsaid first spacer of said second isolation structure; forming an activearea located within said semiconductor substrate between said first andsecond isolation structures; forming a second layer, composed of anelectrically insulative material, filling said first and secondisolation trenches and extending continuously therebetween and abovesaid oxide layer in contact with said first and second spacers of saidrespective first and second isolation structures; and forming a planarupper surface formed from said second layer and said first and secondspacers of said respective first and second isolation structures, andbeing situated above said oxide layer.